Novel Technology Extends Battery Life, Increases Upload Speed, and Reduces Data Corruption

Memory devices come in many forms. From USB sticks, to external hard-drives, to chips implanted directly into smartphones. What makes one better than another is usually a combination of new, groundbreaking materials and the novel device structure. The better the materials, and the way those materials are creatively designed to build the ultimate structure, the better the memory device is. Now, researchers have published a piece in Nature Electronics about their creation of a memory device with improved material and structure and which promises to increase data upload speed, extend smartphone battery life, and reduce data corruption.

Han Wang, associate professor of electrical and computer engineering at the University of Southern California Viterbi School of Engineering, along with postdoctoral scholar Jiangbin Wu, PhD students Hung-Yu Chen and Xiaodong Yan, have achieved this through a concept called the ferroelectric tunneling junction (FTJ).

This new memory device is part of a family known as non-volatile memory devices, meaning they can be unplugged and still retain their data, much like cell phone memory and USB flash drives. Unlike current FTJ devices, this device is comprised of asymmetric metal and semi-metallic graphene materials. By taking these materials and building them into a novel structure, they were  able to exceed the performance of all previously demonstrated FTJs while offering promising prospects for integration with silicon electronics.

Furthermore, the unique ability of these materials to approach atomic-scale thickness can eventually lead to even faster and more energy-efficient FTJ memory down the line. “These materials allow us to build devices that can potentially be scaled to atomic-scale thickness,” Wang said. “This means the voltage required to read, write, and erase data can be drastically reduced which in turn can make the memory electronics much more energy efficient.”

Wang and his fellow researchers hope that with time, their device can be scaled up and may become a replacement not just for the non-volatile memory that we see in cell phones and USB sticks, but also volatile memory like D-RAM storage devices commonly found in computers. In addition, the device may also be engineered to hold multi-bit data states within a single cell, and with its robust endurance and retention, it has promising potential for applications in in-memory computing and other computing hardware.

About the USC Viterbi School of Engineering

Engineering began at the University of Southern California in 1905. Nearly a century later, in 2004, the school was named the USC Viterbi School of Engineering, honoring alumnus Andrew J. Viterbi, inventor of the Viterbi algorithm, a key to cell phone technology and numerous data applications. The school is consistently ranked among the top engineering programs in the world. It enrolls more than 7,000 undergraduate and graduate students, taught by 188 tenured and tenure-track faculty, with more than 90 endowed chairs and professorships. The school offers comprehensive programs in all major areas of engineering, from aerospace and astronautical engineering, to biomedical, chemical, civil and environmental engineering, to computer science and materials science, and to electrical engineering, industrial and systems engineering and mechanical engineering. With annual research expenditures exceeding $207M, the school is home to the Information Science Institute and more than 45 other research centers. Its more than 50,000 alumni span the globe. USC Viterbi is also home to the pioneering distance learning program DEN@Viterbi, ranked as the top such program in the nation the last two years. USC Viterbi is the only engineering school in the nation with three top-10 USNWR rankings: Best Graduate Schools, Best Online Graduate Engineering Programs, and Best Online Information Technology Programs. 

India's EDA industry growing at 30pc annually

Globally, India is amongst the fastest growing markets for EDA tools, along with USA and China. With the EDA market growing here at about 30 percent annually, Hewlett Packard, a leading EDA high performance computing platform solutions provider, is targeting the fast growing chip design centers in India.
On this occasion of the HP Intel Asia-Pacific EDA seminar, Brain Lowe, Alliance Marketing Manager of HP (Cupertino) with Faisal M. Paul, Country Manager (India) – HPC & OSLO of HP (India), spoke to Manu Sharma of CIOL Bureau the on various aspects of the EDA industry. Excerpts:

CIOL: What is EDA and what is its importance?
Brian Lowe: Electronic Design Automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits (ICs). This is sometimes referred to as ECAD (electronic computer-aided design) or just CAD.
EDA is specifically for electronics, and concentrates on EDA used for designing integrated circuits. As chips grow larger and become more complex to design EDA becomes much more important at semiconductor companies.

CIOL: What are the trends in EDA?
BL: EDA computing complexity and very complex chip designs put heavy demands on computing resources such as CPU MIPS and memory. In addition, there is a need for reliable, scalable storage because of the huge chip design database.
There is also a need for setting up data centers and global grid that allow designers to tap into compute servers worldwide. This will allow the compute infrastructure to utilized very efficiently. Besides, this allows the designers and the company to scale the compute resources during various phases of a project.
There is also need to optimize data center design such as power, cooling, floor space, etc., and HP's HPC clustering technologies and blades fit the bill.

CIOL: What is HP's role in the EDA industry?
BL: Electronic product development organizations are constantly challenged to deliver advanced technology to market in less time. HP's focuses on inventiveness creates innovative high-performance technical computing solutions that allow design teams to maximize their EDA productivity.
HP has architected their technical computing solutions to make large memory capacity affordable. This allows engineers to synthesize and simulate larger sections of their designs, thereby maximizing designer productivity.

CIOL: Who is HP targeting in India and why?
Faisal M. Paul: HP provides leadership and innovation in high-performance computing (HPC) solutions for customer EDA design environments. For HP, India is among the fastest growing markets with many chip design firms setting up units in India. We are growing here at 30 percent at par with the USA and China.
HP partners with leading EDA software vendors to leverage HP's internal EDA design expertise and provide direction to HP R&D product groups.

CIOL: What does HP feel about the growing chip design industry in India?
FP: Chips have automated our lives with gizmos and designing this has been a good business proposition for Indian technology firms.
Without any hesitation, we can say that we are among the largest system integration vendors for EDA across the globe. We offer a broad range of Linux-based systems – workstations, servers and blades, together with leading edge IT data center solutions for the design environment.

CIOL: What is HP's innovation in EDA?
BL: As one of the world's largest electronic, R&D, design and manufacturing companies, HP has found innovative ways to employ technologies to address the pressures found in EDA design environments.
In fact, HP was one of the first computer vendors to embrace Linux as a practical and cost-effective alternative to proprietary solutions, including support for a myriad of EDA applications, across a wide range of platforms and flexible clustering solutions.

CIOL: Where does HP's C-class blade role come in?
BL: The HP BladeSystem c-Class enclosure is said to feature the world's fastest midplane at 5TBps of aggregate throughput and the first midplane to support 4X DDR InfiniBand, the industry's fastest blade server interconnect, which delivers up to 20GBps bandwidth in each direction especially meant for high performance computing for the chip design companies.

CIOL: Where does HP stand in the blade industry today?
BL: Following the introduction of HP C Class blade for high-performance computing during the third quarter of 2006, HP has outperformed all competitors with 85 percent growth. We are at the No. 1 position according to IDC Server tracker in Q4- 2006 in x86 Blades report, followed by IBM and Dell.

CIOL: How does the chip design automation in India look like?
FP: The Indian product market has already crossed the $1 billion mark. The chip automated our lives with electronic gizmos and has been a good business proposition for Indian technology firms. Now, we are moving towards the next step, designing tools that automate the chip designing process itself.
This growth is likely to accelerate with more players entering the fray in the coming years as electronics consumption goes up significantly.
At present, there are about seven major EDA companies, both multinational and Indian, operating in the country. Cadence, Mentor Graphics, Magma, Synopsys, Circuit Sutra, Sequence Design and SoftJin are all reporting growth. The India Semiconductor Association (ISA) expects more domestic players to start providing EDA tools to chip designers.